The present invention relates to a switching power supply that includes a plurality of inductors and changes the connecting relation of the inductors during the operations thereof.
A configuration example of a conventional switching power supply will be described below with reference to FIG. 13. FIG. 13 is a block circuit diagram of a buck DC-DC converter that conducts a pulse width modulation (hereinafter referred to as a “PWM”) to generate output voltage Eo from input voltage Ei and feeds output voltage Eo to load RL. The buck DC-DC converter includes error amplifier 1 formed of an operational amplifier, oscillator 2, PWM comparator 3, P-channel metal-oxide-semiconductor field-effect transistor (hereinafter referred to as “MOSFET”) Q1 working for a switching device (hereinafter the switching device will be designated by Q1), commutation diode D1, diver circuit 4 that drives switching device Q1 based on the output from PWM comparator 3, inductor L1, output capacitor Co, resistors R1 and R2 working for a feedback means for voltage setting, reference voltage supply 5 that generates reference voltage Vref, and DC input power supply 6 that feeds input voltage Ei.
Reference voltage Vref is fed to the non-inverting input terminal of error amplifier 1. Feedback signal VFB obtained by dividing output voltage Eo with resistors R1 and R2 is fed to the inverting input terminal of error amplifier 1. Resistor R3 and capacitor C1 are connected between the output terminal and the inverting input terminal of error amplifier 1 for phase compensation. Output signal Verr from error amplifier 1 is fed to the non-inverting input terminal of PWM comparator 3. Output signal Vosc from oscillator 2 is fed to the inverting input terminal of PWM comparator 3.
Output signal Vosc from oscillator 2 is a triangular wave, a sawtooth wave or a sinusoidal wave. In FIG. 13, output signal Vosc is illustrated by a triangular wave exemplary. PWM comparator 3 compares output signal Verr from error amplifier 1 with triangular wave Vosc. When the signal level of triangular wave Vosc is lower than the signal level of output signal Verr, PWM comparator 3 sets the PWM signal thereof at a high level (hereinafter referred to as an “H-level”) and feeds the H-level PWM signal to driver circuit 4. When the signal level of triangular wave Vosc is equal to or higher than the signal level of output signal Verr, PWM comparator 3 sets the PWM signal thereof at a low level (hereinafter referred to as an “L-level”) and feeds the L-level PWM signal to driver circuit 4.
The drain of switching device Q1 and the cathode of diode D1 are connected to each other. The drain of switching device Q1 and the cathode of diode D1 are connected also to the first end of inductor L1. The source of switching device Q1 is connected to the high-potential-side terminal of DC input power supply 6. The anode of diode D1 is connected to the low-potential-side terminal of DC input power supply 6. The second end of inductor L1 is connected to load RL. Output capacitor Co and a series circuit consisting of resistors R1 and R2 are connected in parallel to each other between the second end of inductor L1 and the low-potential-side terminal of DC input power supply 6. The potential at the connection point of resistors R1 and R2 is fed to the inverting input terminal of error amplifier 1 as feedback signal VFB.
Now the operations of the DC-DC converter will be briefly described below. Error amplifier 1 feeds error signal Verr obtained by amplifying the difference between reference voltage Vref and feedback signal VFB to PWM comparator 3. PWM comparator 3 compares error signal Verr and triangular wave Vosc to each other and feeds a switching signal (PWM signal) to switching device Q1 via driver circuit 4. The PWM signal is a rectangular wave signal having a certain period but the H/L ratio in one period changes based on the output from error amplifier 1. As (Vref−VFB) is larger, PWM comparator 3 generates a rectangular wave that makes the ON-period (conduction-period) of switching device Q1 in one switching period longer to accumulate more energy in inductor L1 and further to keep output voltage Eo at a certain value. As (Vref−VFB) is smaller, PWM comparator 3 generates a rectangular wave that makes the ON-period (conduction-period) of switching device Q1 in one switching period shorter to accumulate less energy in inductor L1 and further to keep output voltage Eo at a certain value. Resistors R1 and R2 constitute a feedback signal generator circuit. Resistor R3, capacitor C1, error amplifier 1, and reference voltage supply 5 constitute an error amplifier circuit.
If the ON-period and OFF-period of switching device Q1 are represented by Ton and Toff, respectively, and the switching period by Ts (=Ton+Toff), the input voltage value Ei and the output voltage value Eo of the conventional buck DC-DC converter will be related with each other by the following formula (1).Eo=(Ton/Ts)Ei=D·Ei  (1)
Here, D=Ton/Ts is an ON-time ratio, that is the ratio of the ON-period Ton to the switching period Ts. Although the ON-time ratio D may be any value between 0 and 1 according to the formula (1), an ON-time ratio D close to the upper limit 1 and an ON-time ratio D close to the lower limit 0 are restricted in the practical circuits.
In other words, PWM comparator 3 compares error signal Verr with triangular wave Vosc and generates the switching signal (PWM signal). Since the upper and lower limits of the ON-time ratio D are determined by the upper and lower limits of triangular wave Vosc, it is difficult to precisely control the minute time widths of the ON-period Ton and the OFF-period Toff due to the adverse effects of the noises contained in triangular wave Vosc and error signal Verr. Therefore, there remains no choice but to limit the value of the ON-time ratio D.
Recently, the switching frequency has been becoming higher and higher. When the switching frequency is 1 MHz or higher, it is necessary to control the time width of several tens ns or shorter as the minute time widths described above. The adverse effects of the delay times caused by various circuit elements on the time width described above are not ignorable. Sometimes, the pulse itself vanishes. Therefore, it is very much necessary to set upper and lower limits for the ON-time ratio D. When the ON-time ratio D is close to 1 for a long time, the current flowing through inductor L1 keeps increasing, resulting in an overcurrent. To prevent the overcurrent from causing, an upper limit is set for the ON-time ratio D usually. Usually, the ON-time ratio D is limited to be from 0.1 to 0.9.
The upper and lower limits of the ON-time ratio D are limited also in the other types of DC-DC converters other than the buck DC-DC converter. A DC-DC converter of an inversion type and a DC-DC converter of a boost type are disclosed in the following Patent Document 1 for obtaining the upper limit of the ON-time ratio D, that is for obtaining a high output voltage. The DC-DC converters disclosed in Japanese Unexamined Patent Application Publication No. Hei. 4 (1992)-96649 employ two inductors (reactors) and connect the inductors in parallel while the switching device is ON and in series while the switching device is OFF so that a high output voltage may be obtained without setting the ON-time ratio D in the vicinity of the upper limit thereof.
However, it is difficult for the conventional technique to obtain a low output voltage corresponding to an ON-time ratio D close to the lower limit value. The above-identified reference discloses how to obtain a high output voltage but nothing on obtaining a low output voltage. Recently, the power supply voltage for microprocessors and such large scale LSIs has been lowered. For meeting the recent demands, it is necessary for the ON-time ratio D of the DC-DC converter to close to the lower limit thereof. However, it is difficult for the conventional DC-DC converter to make the ON-time ratio D thereof close to the lower limit thereof.
For obtaining a low output voltage, it may be effective to connect a plurality of conventional DC-DC converters in series as shown in FIG. 15 so that the total step down ratio (Eo/Ei) may be lowered. However, this technique causes the problems described below. The fundamental structure of a single-stage DC-DC converter obtained by removing the control circuit including the feedback system from the circuit shown in FIG. 13 is shown in FIG. 14. The DC-DC converter shown in FIG. 15 connects two single-stage DC-DC converters shown in FIG. 14 in series.
In detail, the DC-DC converter shown in FIG. 15 connects, in the subsequent stage of the DC-DC converter shown in FIG. 14, a DC-DC converter including switching device Q2, inductor L2, commutation diode D2, and output capacitor Co2. The DC-DC converter shown in FIG. 15 steps down output voltage Eo1 fed across capacitor Co1 of the DC-DC converter in the first stage with the DC-DC converter in the subsequent stage to obtain low output voltage Eo and to feed low output voltage Eo to load RL. The control circuit is not shown in FIG. 15. It is necessary for the technique that connects a plurality of DC-DC converters in series as shown in FIG. 15 to employ full sets of converter circuits. Therefore, the technique that connects a plurality of DC-DC converters in series as shown in FIG. 15 is not advantageous for reducing the manufacturing costs and the size of the resulting DC-DC converter. Especially, since it is necessary to dispose an output capacitor for each of the DC-DC converters and since it is necessary for the capacitance of the output capacitor to be large to some extents, the disposition of a plurality of output capacitors greatly affects adversely.
In view of the foregoing, it would be desirable to obviate the problems described above. It would be also desirable to provide a switching power supply that facilitates preventing the circuit scale thereof from being enlarged, preventing the number of the large-capacity capacitors from increasing, and obtaining a low output voltage.